module ysyx_22040213_IDReg(
	input clk,
	input rst,
	input flush,
	
	//special inst reg
	input IF_ready_go,
	output reg if_inst_valid,

	//end
	input IF_to_ID_valid,
	input o_bub_ID_ready_go,
	input EXE_allow_in,
	
	output ID_allow_in,
	output ID_to_EXE_valid,
	output reg ID_valid,

	input [63:0] dnpc,
	input [63:0] pc,
//	input pc_ready_go,
	input [63:0] i_id_inst,
	input [63:0] i_id_pc_link,
	output reg [63:0] o_if_dnpc,
	output reg [63:0] o_if_pc,
	output reg [63:0] o_id_inst_sram,
	output reg [63:0] o_id_pc_link,
 	//DIFFTEST 
	input i_id_diff_clint_trap,
	output reg o_id_diff_clint_trap
);
/* verilator lint_off UNUSED*/
//	reg ID_valid;

	wire ID_ready_go = o_bub_ID_ready_go;

	assign ID_allow_in = !ID_valid || ID_ready_go && EXE_allow_in;
	assign ID_to_EXE_valid = ID_valid && ID_ready_go;

	always @(posedge clk)begin
	  if(rst)begin
	    ID_valid <= 1'b0;
	  end
	  else if(ID_allow_in)begin
	    ID_valid <= IF_to_ID_valid;
	  end
	  
	  if(rst)begin
	    if_inst_valid <= 1'b0;
	  end
	  else if (IF_ready_go && !ID_allow_in)begin //instram data valid
	    if_inst_valid <= IF_to_ID_valid;
	  end else begin
	    if_inst_valid <= 1'b0;
	  end
//	  if(if_inst_valid)begin
//	    o_id_inst_dram <= if_inst;
//	  end else begin
//	    o_id_inst_dram <= o_id_inst_sram;
//	  end
	end

	wire w_en;
	assign w_en = IF_to_ID_valid && ID_allow_in;

	//AXI
	reg [63:0] if_inst = 64'h13;
		
	Reg #(64, 64'h13) i0 (clk, rst || (flush && w_en), i_id_inst, if_inst, IF_to_ID_valid && ~if_inst_valid);
	
	Reg #(64, 64'b0 ) i1 (clk, rst || (flush && w_en), i_id_pc_link, o_id_pc_link, w_en);

	Reg #(64, 64'h0 ) i3  (clk, rst , dnpc, o_if_dnpc, w_en);
	
	Reg #(64, 64'h0 ) i5  (clk, rst , pc, o_if_pc, w_en);

	Reg #(1, 1'b0 ) i6  (clk, rst , i_id_diff_clint_trap, o_id_diff_clint_trap, w_en);

	wire [63:0] o_id_inst_ram = if_inst_valid ? if_inst : o_id_inst_sram;

	// do not consider axi
	reg[63:0] test_inst;
	Reg #(64, 64'h13 ) i2 (clk, rst || (flush && w_en), i_id_inst , test_inst, w_en);
	Reg #(64, 64'h13 ) i4 (clk, rst || (flush && w_en), {64{~if_inst_valid}} & i_id_inst |{64{if_inst_valid}} & o_id_inst_ram, o_id_inst_sram, w_en);  //the real output
	wire diff;
	assign diff = ~(test_inst == o_id_inst_sram);	
endmodule
